vextractbm

Vector Extract Byte Mask

vextractbm RA, vB

Extracts bit 0 of each byte element from a VSR into a GPR.

Encoding

Binary Layout

4

0:5

RT

6:10

8

11:15

VRB

16:20

1602

21:31

 

Format VX-form

Opcode 0x10080642

Extension VMX (AltiVec)

Operands

• RA
  Target
• vB
  Source
• RT
  Target General Purpose Register
• VRB
  Source Vector Register

Example

vextractbm r4, vb

Registers Altered

MSR

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The contents of bit 0 of each byte element of VSR[VRB+32] are concatenated and placed into bits 48:63 of GPR[RT]. Bits 0:47 of GPR[RT] are set to 0.

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 15
    GPR[RT].bit[48+i] ← VSR[VRB+32].byte[i].bit[0]
end
GPR[RT].bit[0:47] ← 0

Programming Note

This instruction is used to extract the least significant bit from each byte of a vector register and pack them into the upper half of a general-purpose register. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The lower half of the target GPR is always zeroed out, so be cautious if you need to preserve existing data in that portion.