vgnb

Vector Gather Non-Zero Bytes

vgnb vD, vB, UIM

Gathers every Nth bit from a vector register and places it into a general-purpose register.

Encoding

Binary Layout

0:5

6:10

UIM

11:15

16:20

1228

21:31

Format VX-form

Opcode 0x100004CC

Extension VMX (AltiVec)

Operands

vD
Target
vB
Source
UIM
Stream
RT
Target General Purpose Register
VRB
Source Vector Register
N
Gather interval (2 to 7)

Example

vgnb vd, vb, uim

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Gathers every Nth bit (where N is 2-7 as specified by UIM) from vector register vB and packs them into a 64-bit general-purpose register. The bits are gathered starting from bit 0 of vB and compacted into the lower bits of the result; unused upper bits are zeroed. This is a VMX extension instruction with no condition register or status flag updates.

Operation

N ← UIM
result ← 0
bit_pos ← 0
for i in 0 to 127 by N do
  if i < 128 then
    result[bit_pos] ← vB[i]
    bit_pos ← bit_pos + 1
vD[0:63] ← result

Programming Note

N must be between 2 and 7 inclusive.