xvnmsubadp

VSX Vector Negative Multiply-Subtract Type-A Double-Precision

xvnmsubadp XT,XA,XB

Performs a negative multiply-subtract operation on double-precision floating-point elements.

Details

For each integer value i from 0 to 1, the instruction performs the following operations: multiplies src1 by src3, negates src2, adds the result to the product, normalizes the sum, rounds it to double precision, and places the final result into VSR[XT].

Pseudocode Operation

if MSR.VSX=0 then VSX_Unavailable()

ex_flag ←0b0
do i = 0 to 1
    reset_xflags()
    src1 ←bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[i])
    src2 ←bfp_CONVERT_FROM_BFP64(VSR[32×TX+T].dword[i])
    src3 ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[i])

    v   ←bfp_MULTIPLY_ADD(src1,src3,bfp_NEGATE(src2))
    rnd ←bfp_NEGATE(bfp_ROUND_TO_BFP64(FPSCR.RN,v))
    vresult.dword[i] ←bfp64_CONVERT_FROM_BFP(rnd)

    if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
    if vximz_flag=1 then SetFX(FPSCR.VXIMZ)
    if vxisi_flag=1 then SetFX(FPSCR.VXISI)
    if ox_flag=1 then SetFX(FPSCR.OX)
    if ux_flag=1 then SetFX(FPSCR.UX)
    if xx_flag=1 then SetFX(FPSCR.XX)

    ex_flag ←ex_flag | (FPSCR.VE & vxsnan_flag) | (FPSCR.VE & vximz_flag) | (FPSCR.VE & vxisi_flag) | (FPSCR.OE & ox_flag) | (FPSCR.UE & ux_flag) | (FPSCR.XE & xx_flag)
end

if ex_flag=0 then VSR[32×TX+T] ←vresult

Programming Note

This instruction is used for performing vectorized negative multiply-subtract operations on double-precision floating-point numbers. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid exceptions. Be cautious of potential overflow and underflow conditions, as indicated by the exception flags. The operation processes two elements at a time, so ensure your data is correctly aligned for optimal performance.

Example

xvnmsubadp vs1, vs2, vs3

Encoding

Binary Layout
60
0
XT
6
XA
11
XB
16
1928
21
 
Format XX3-form
Opcode 0xF0000788
Extension VSX
Registers Altered FPSCR, VXSNAN, VXIMZ, Vxisi, OX, UX, XX

Operands

  • XT
    Target Vector Register
  • XA
    Source Vector Register
  • XB
    Source Vector Register