xsmulsp

VSX Scalar Multiply Single-Precision

xsmulsp XT, XA, XB

Multiplies two single-precision floating-point numbers and stores the result in a doubleword element of a VSX register.

Details

The xsmulsp instruction multiplies the contents of two VSX registers (XA and XB) containing single-precision floating-point numbers, producing a product with unbounded range and precision. The product is normalized and rounded to single-precision format using the rounding mode specified by RN. The result is placed into doubleword element 0 of VSR[XT] in double-precision format, and doubleword element 1 of VSR[XT] is set to zero.

Pseudocode Operation

if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src1 ←bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[0])
src2 ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[0])
v ←bfp_MULTIPLY(src1,src2)
rnd ←bfp_ROUND_TO_BFP32(FPSCR.RN,v)
result32 ←bfp32_CONVERT_FROM_BFP(rnd)
result64 ←bfp64_CONVERT_FROM_BFP(rnd)
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if vximz_flag=1 then SetFX(FPSCR.VXIMZ)
if ox_flag=1 then SetFX(FPSCR.OX)
if ux_flag=1 then SetFX(FPSCR.UX)
if xx_flag=1 then SetFX(FPSCR.XX)
vex_flag ←FPSCR.VE & vx_flag
if vex_flag=0 then do
    VSR[32×TX+T].dword[0] ←result64
    VSR[32×TX+T].dword[1] ←0x0000_0000_0000_0000
    FPSCR.FPRF ←fprf_CLASS_BFP32(result32)
    FPSCR.FR  ←inc_flag
    FPSCR.FI  ←xx_flag
end else do
    FPSCR.FR  ←0b0
    FPSCR.FI  ←0b0
end

Programming Note

Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.

Example

xsmulsp vs1, vs2, vs3

Encoding

Binary Layout
60
0
XT
6
XA
11
XB
16
16
21
 
Format XX3-form
Opcode 0xF0000010
Extension VSX
Registers Altered FPSCR, VSR[XT]

Operands

  • XT
    Target
  • XA
    Src A
  • XB
    Src B