xsmulsp

VSX Scalar Multiply Single-Precision

xsmulsp XT, XA, XB

Multiplies two single-precision floating-point numbers and stores the result in a doubleword element of a VSX register.

Encoding

Binary Layout

60

0:5

XT

6:10

XA

11:15

XB

16:20

16

21:31

 

Format XX3-form

Opcode 0xF0000080

Extension VSX

Operands

• XT
  Target
• XA
  Src A
• XB
  Src B

Example

xsmulsp vs1, vs2, vs3

Registers Altered

FPSCR, VSR[XT]

Related

More in VSX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Multiplies the single-precision floating-point value in the lower 32 bits of XA by the single-precision floating-point value in the lower 32 bits of XB, produces a single-precision result, and stores it in the lower 32 bits of XT. The upper 32 bits of XT are set to zero. FPSCR is updated with the exception flags and result class from the operation.

Operation

SP_A ← XA[32:63]
SP_B ← XB[32:63]
product ← SPFP_multiply(SP_A, SP_B)
XT[0:31] ← 0
XT[32:63] ← product
FPSCR ← update_fpscr(FPSCR, product)

Programming Note

Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.