xvmuldp

VSX Vector Multiply Double-Precision

xvmuldp XT, XA, XB

Multiplies two double-precision floating-point numbers in vector registers and stores the result.

Encoding

Binary Layout

60

0:5

XT

6:10

XA

11:15

XB

16:20

112

21:31

 

Format XX3-form

Opcode 0xF0000380

Extension VSX

Operands

• XT
  Target
• XA
  Src A
• XB
  Src B

Example

xvmuldp vs1, vs2, vs3

Registers Altered

FPSCR

Related

More in VSX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

VSX Vector Multiply Double-Precision multiplies two double-precision floating-point elements from VSX registers XA and XB, storing the results in VSX register XT. This VSX category instruction processes two 64-bit elements in parallel and may update FPSCR with floating-point exception flags.

Operation

XT[0:63] ← XA[0:63] × XB[0:63]
XT[64:127] ← XA[64:127] × XB[64:127]

Programming Note

The xvmuldp instruction performs element-wise multiplication of double-precision floating-point values in VSX registers. Ensure that the input vectors are properly aligned to avoid alignment faults. Be cautious with NaN and infinity handling, as they follow specific rules for propagation and sign determination. This instruction operates at user privilege level.