xvcvspuxds

Vector Convert with round to zero Single-Precision to Unsigned Doubleword format

xvcvspuxds XT,XB

Converts a single-precision floating-point value to an unsigned doubleword integer, rounding according to the current rounding mode.

Encoding

Binary Layout
60
0:5
XT
6:10
/
11:15
XB
16:20
1568
21:31
 
Format XX2-form
Opcode 0xF0000620
Extension VSX

Operands

  • XT
    Target Vector Register
  • XB
    Source Vector Register
  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Source Vector Register

Example

xvcvspuxds vs1, vs3

Registers Altered

FPSCR, VXSNAN, VXCVI, XX

Related

More in VSX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Converts single-precision floating-point elements in XB to unsigned 64-bit integer elements in XT, using the current rounding mode. This is a VSX instruction that processes elements independently. No condition registers or status fields are affected.

Operation

for i in 0 to 1 do
  XT[i*64:(i+1)*64-1] ← CVTSP_TO_UI64(XB[i*32:(i+1)*32-1])
end for

Programming Note

xvcvspuxds rounds using Round towards Zero rounding mode. For other rounding modes, software must use a Round to Single-Precision Integer instruction that corresponds to the desired rounding mode, including xvrspic which uses the rounding mode specified by RN.