xvcvspuxds

Vector Convert with round to zero Single-Precision to Unsigned Doubleword format

xvcvspuxds XT,XB

Converts a single-precision floating-point value to an unsigned doubleword integer, rounding according to the current rounding mode.

Details

The xvcvspuxds instruction converts a single-precision floating-point value in word element i of VSR[XB] (where i∈{0,2}) to an unsigned doubleword integer and places it in doubleword element i of VSR[XT] (where i∈{0,1}). The conversion follows the current rounding mode.

Pseudocode Operation

for i = {0, 2} do
    src <- VSR[XB][i]
    if src is a QNaN then
        T(Nmin), fx(VXCVI)
    else if src is a SNaN then
        T(Nmin), fx(VXCVI), fx(VXSNAN)
    else if src ≤ Nmin-1 then
        T(Nmin), fx(VXCVI)
    else if Nmin-1 < src < Nmin then
        if FPSCR.VE = 0 then
            T(Nmin), fx(XX)
        else
            fx(XX), error()
    else if src = Nmin then
        T(Nmin)
    else if Nmin < src < Nmax then
        if FPSCR.XE = 0 then
            T(f2i(trunc(src))), fx(XX)
        else
            fx(XX), error()
    else if src = Nmax then
        T(Nmax)
    else if Nmax < src < Nmax+1 then
        if FPSCR.VE = 0 then
            T(Nmax), fx(XX)
        else
            fx(XX), error()
    else if src ≥ Nmax+1 then
        T(Nmin), fx(VXCVI)
    end if
end for

Programming Note

xvcvspuxds rounds using Round towards Zero rounding mode. For other rounding modes, software must use a Round to Single-Precision Integer instruction that corresponds to the desired rounding mode, including xvrspic which uses the rounding mode specified by RN.

Example

xvcvspuxds vs1, vs3

Encoding

Binary Layout
60
0
XT
6
/
11
XB
16
1568
21
 
Format XX2-form
Opcode 0xF0000620
Extension VSX
Registers Altered FPSCR, VXSNAN, VXCVI, XX

Operands

  • XT
    Target Vector Register
  • XB
    Source Vector Register
  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Source Vector Register