vaddshs

Vector Add Signed Halfword Saturate

vaddshs vD, vA, vB

Adds the contents of two vector registers and saturates the result if it overflows.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

832

21:31

Format VX-form

Opcode 0x10000340

Extension VMX (AltiVec)

Operands

vD
Target
vA
Src A
vB
Src B
VRT
Target Vector Register
VRA
Source Vector Register
VRB
Source Vector Register

Example

vaddshs vd, va, vb

Registers Altered

VSCR (SAT)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For vaddshs, each halfword element in VSR[VRA+32] is added to the corresponding halfword element in VSR[VRB+32]. The result is saturated if it exceeds the range of a signed 16-bit integer.

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 7
    src1 ←EXTS(VSR[VRA+32].hword[i])
    src2 ←EXTS(VSR[VRB+32].hword[i])
    VSR[VRT+32].hword[i] ←si16_CLAMP(src1 + src2)
end

Programming Note

vaddshs is used for adding signed halfwords with saturation. Ensure that the vector facility (MSR.VEC) is enabled; otherwise, a Vector_Unavailable exception will occur. The operation saturates results if they exceed the 16-bit signed integer range, preventing overflow. This instruction operates on elements in the upper half of the VSX registers.