srw

Shift Right Word

srw RA, RS, RB

Performs a logical right shift (zeros shifted in) on a 32-bit word.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

536

21:30

Format X-form

Opcode 0x7C000430

Extension Base

Operands

RA
Target Register
RS
Source Register
RB
Shift Amount Register

Example

srw r3, r4, r5

// r3 = r4 >> r5 (Unsigned 32-bit).

Registers Altered

CR0

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Logically shift the 32-bit word in RS right by the number of bits specified in RB[27:31] (only the low 5 bits are used), filling vacated positions with zeros. The result is placed in RA. If Rc=1, CR0 is updated based on the result.

Operation

n ← RB[27:31]
if n < 32 then
  RA[0:63] ← EXTZ(RS[32:63] >> n, 32)
else
  RA[0:63] ← 0
if Rc = 1 then
  CR0 ← (RA = 0) || LT || GT || SO

Programming Note

When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.

srw