srw

Shift Right Word

srw RA, RS, RB

Performs a logical right shift (zeros shifted in) on a 32-bit word.

Details

The srw instruction performs a right shift on the lower 32 bits of the contents of register RS by the number of bits specified in the lower 5 bits of register RB. The result is placed into register RA.

Pseudocode Operation

n <- RB[58:63]; RA <- ROTL32(RS, 64-n) & MASK(n, 31)

Programming Note

When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.

Example

srw r3, r4, r5

Encoding

Binary Layout
31
0
RS
6
RA
11
RB
16
536
21
Rc
31
 
Format X-form
Opcode 0x7C000438
Extension Base
Registers Altered CR0

Operands

  • RA
    Target Register
  • RS
    Source Register
  • RB
    Shift Amount Register