vextractqm

Vector Extract Quadword Mask

vextractqm RA, vB

Extracts the least significant bit of a vector register and places it into a general-purpose register.

Encoding

Binary Layout

4

0:5

RA

6:10

0

11:15

vB

16:20

1858

21:31

 

Format VX-form

Opcode 0x100C0642

Extension VMX (AltiVec)

Operands

• RA
  Target
• vB
  Source
• RT
  Target General Purpose Register
• VRB
  Source Vector Register

Example

vextractqm r4, vb

Registers Altered

MSR

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The contents of bit 0 of VSR[VRB+32] are placed into bit 63 of GPR[RT]. Bits 0:62 of GPR[RT] are set to 0.

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
GPR[RT] ← EXTZ64(VSR[VRB+32].bit[0])

Programming Note

This instruction extracts the least significant bit from a vector register and places it into the most significant bit of a general-purpose register, setting all other bits in the GPR to zero. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register before using this instruction. This operation is useful for extracting flags or status information from vector operations.