vdivsd

Vector Divide Signed Doubleword

vdivsd VRT,VRA,VRB

Divides the contents of two vector registers and updates the result in another vector register.

Details

For vdivsd, each doubleword element in VSR[VRA+32] is divided by the corresponding doubleword element in VSR[VRB+32]. The quotient is placed into the corresponding doubleword element in VSR[VRT+32].

Pseudocode Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 1
    dividend ←EXTS(VSR[VRA+32].dword[i])
    divisor  ←EXTS(VSR[VRB+32].dword[i])
    VSR[VRT+32].dword[i] ←CHOP64(dividend ÷ divisor)
end

Programming Note

This instruction performs element-wise division of signed doublewords. Ensure that the vector facility is enabled (MSR.VEC=1) to avoid exceptions. Handle potential division by zero and overflow conditions in your application logic.

Example

vdivsd v1, v2, v3

Encoding

Binary Layout
0
0
VRT
6
VRA
11
VRB
16
 
Format VX-form
Opcode 0x100001CB
Extension VMX (AltiVec)
Registers Altered None

Operands

  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Source Vector Register