vadduws

Vector Add Unsigned Word Saturate

vadduws vD, vA, vB

Adds the contents of two vector registers and saturates the result if it exceeds 32 bits.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

640

21:31

Format VX-form

Opcode 0x10000280

Extension VMX (AltiVec)

Operands

vD
Target
vA
Src A
vB
Src B
VRT
Target Vector Register
VRA
Source Vector Register
VRB
Source Vector Register

Example

vadduws vd, va, vb

Registers Altered

VSCR.SAT

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For vadduws, each word element in VSR[VRA+32] is added to the corresponding word element in VSR[VRB+32]. If the sum exceeds 2^32 - 1, it saturates to 2^32 - 1 and sets the SAT field in VSCR.

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    src1 ←EXTZ(VSR[VRA+32].word[i])
    src2 ←EXTZ(VSR[VRB+32].word[i])

    VSR[VRT+32].word[i] ←ui32_CLAMP(src1 + src2)
end

Programming Note

vadduws is used for adding unsigned 32-bit integers in vector registers with saturation. Ensure that the Vector Facility (MSR.VEC) is enabled; otherwise, a Vector_Unavailable exception will occur. The operation saturates sums exceeding 2^32 - 1 and sets the SAT field in VSCR to indicate saturation occurred.