lxvp

Load VSX Vector Pair

lxvp XT, DQ(RA)

Loads a double quadword from memory into two VSX registers.

Encoding

Binary Layout

6

Tp

TX

RA

DQ

0

 

Format DQ-form

Opcode 0x18000000

Extension VSX

Operands

• XT
  Target Even VSR
• DQ
  Offset
• RA
  Base
• XTp
  Target Vector-Specific Register
• disp
  Displacement field
• VRT
  Target Vector-Specific Register
• EA
  Effective Address

Example

lxvp vs1, 0(r4)

Registers Altered

MSR

Related

More in VSX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Loads a 256-bit (32-byte) aligned vector pair from memory at the effective address (RA + DQ), storing the first 128 bits into XT and the second 128 bits into XT+1. DQ is a 4-bit field that specifies the offset in units of 16 bytes, requiring 16-byte alignment. Requires VSX support.

Operation

EA ← (RA) + (DQ << 4); XT ← [EA]; (XT+1) ← [EA+16]

Programming Note

For best performance, EA should be word-aligned.