xsdivdp

VSX Scalar Divide Double-Precision

xsdivdp XT,XA,XB

Divides the double-precision floating-point value in VSR[XA] by the double-precision floating-point value in VSR[XB].

Encoding

Binary Layout

111100

000000

Format XX3-form

Opcode 0xF00001C0

Extension VSX

Operands

XT
Target Vector-Scalar Register
XA
Source Vector-Scalar Register
XB
Source Vector-Scalar Register

Example

xsdivdp vs1, vs2, vs3

Registers Altered

FPSCR FPRF FR FI FX OX UX ZX XX VXSNAN VXIDI VXZDZ

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Divides the scalar double-precision floating-point value in VSR[XA] by the scalar double-precision floating-point value in VSR[XB], storing the result in VSR[XT]. The operation follows IEEE 754 semantics; FPSCR is updated with exception flags and the result sign/exponent. This VSX instruction requires the VSX extension.

Operation

XT ← VSR[XA] ÷ VSR[XB]
FPSCR ← updated with exception flags and rounding

Programming Note

The xsdivdp instruction is used for dividing double-precision floating-point numbers. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid exceptions. Handle special cases like NaNs and infinities by checking the FPSCR flags after execution. The result is rounded according to the rounding mode set in FPSCR.RN.