vmulhsd

Vector Multiply High Signed Doubleword

vmulhsd vD, vA, vB

Multiplies the signed doublewords of two vector registers and stores the high-order 64 bits of each product in a result vector register.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

968

21:31

Format VX-form

Opcode 0x100003C9

Extension VMX (AltiVec)

Operands

vD
Target
vA
Src A
vB
Src B
VRT
Target Vector Register
VRA
Source Vector Register
VRB
Source Vector Register

Example

vmulhsd vd, va, vb

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For vmulhsd, the signed integer value in doubleword element i of VSR[VRA+32] is multiplied by the signed integer value in doubleword element i of VSR[VRB+32]. The high-order 64 bits of the 128-bit product are placed into doubleword element i of VSR[VRT+32].

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 1
    src1 ←EXTS(VSR[VRA+32].dword[i])
    src2 ←EXTS(VSR[VRB+32].dword[i])
    VSR[VRT+32].dword[i] ←CHOP64((src1 × src2) >> 64)
end

Programming Note

This instruction is used for high-precision multiplication of signed doublewords. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation is performed on each pair of doubleword elements from the input vectors, and only the high 64 bits of the 128-bit product are stored in the result vector. Be cautious of overflow conditions as they can lead to unexpected results.