dmulq

Decimal Multiply Quad-Precision

dmulq vD, vA, vB

Multiplies two 128-bit DFP numbers.

Encoding

Binary Layout

63

0:5

vD

6:10

vA

11:15

vB

16:20

34

21:30

/

31

 

Format X-form

Opcode 0xFC000044

Extension Decimal Floating-Point

Operands

• vD
  Target
• vA
  Src A
• vB
  Src B

Example

dmulq vd, va, vb

Registers Altered

FPSCR

Related

More in Decimal Floating-Point

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Multiplies two 128-bit Decimal Floating-Point values in vA and vB, storing the result in vD. The operation follows DFP semantics, respecting the current rounding mode in FPSCR. The result may be rounded or may signal overflow, underflow, or inexact exception. The FPSCR is updated with exception flags.

Operation

vD ← vA × vB (DFP arithmetic)
FPSCR ← updated with exception flags (XX, ZX, UX, OX, IE)

Programming Note

The dmulq instruction is used for multiplying two decimal floating-point numbers with quad-precision. Ensure that the operands are correctly aligned and formatted as DFP. The result's precision is controlled by the FPSCR register, specifically the DRN bits. Be aware of potential rounding errors based on the target format precision.