vaddubm

Vector Add Unsigned Byte Modulo

vaddubm vD, vA, vB

Adds the contents of two vector registers and updates the result in another vector register, modulo operation for bytes.

Details

For vaddubm, each byte element of VSR[VRA+32] is added to the corresponding byte element of VSR[VRB+32], and the low-order 8 bits of the result are placed into the corresponding byte element of VSR[VRT+32].

Pseudocode Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 15
    src1 ←EXTZ(VSR[VRA+32].byte[i])
    src2 ←EXTZ(VSR[VRB+32].byte[i])
    VSR[VRT+32].byte[i] ←CHOP8(src1 + src2)
end

Programming Note

vaddubm can be used for unsigned or signed integers.

Example

vaddubm vd, va, vb

Encoding

Binary Layout
4
0
vD
6
vA
30
vB
31
0
 
Format VX-form
Opcode 0x10000000
Extension VMX (AltiVec)
Registers Altered MSR

Operands

  • vD
    Target
  • vA
    Src A
  • vB
    Src B
  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Source Vector Register