slw

Shift Left Word

slw RT,RA,RB

Shifts a 32-bit register left by the amount specified in RB.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

21:30

Format X-form

Opcode 0x7C000030

Extension Base

Operands

RA
Target Register
RS
Source Register
RB
Shift Amount Register
RT
Target General Purpose Register

Example

slw r3, r4, r5

// r3 = r4 << r5 (32-bit).

Registers Altered

CR0

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The contents of the low-order 32 bits of register RS are shifted left the number of bits specified by (RB)58:63. Bits shifted out of position 32 are lost. Zeros are supplied to the vacated positions on the right. The 32-bit result is placed into RA32:63. RA0:31 are set to zero. Shift amounts from 32 to 63 give a zero result.

Operation

n ← (RB)59:63
r ← ROTL32((RS)32:63, n)
if (RB)58 = 0 then
    m ← MASK(32, 63-n)
else
    m ← 640
RA ← r & m

Programming Note

When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.

slw