lmw

Load Multiple Word

lmw RT, D(RA)

Loads words from memory into registers RT through R31 (Context Switch).

Details

Loads a sequence of words from memory starting at address (RA + D) into GPRs RT through R31, incrementing the address by 4 bytes for each register. This instruction is part of the Base ISA and does not update condition registers; it may be used for context switching.

Pseudocode Operation

if RA = 0 then EA ← 0 + D else EA ← RA + D
for i ← 0 to (31 - RT) do
  GPRC[RT+i] ← MEM[EA+4*i : EA+4*i+31]
end for

Programming Note

This instruction is not supported in Little-Endian mode. If it is executed in Little-Endian mode, the system alignment error handler is invoked.

Example

lmw r3, 0(r4)

Encoding

Binary Layout
46
0
RT
6
RA
11
D
16
 
Format D-form
Opcode 0xB8000000
Extension Base

Operands

  • RT
    Start Register
  • D
    Displacement
  • RA
    Base