vaddudm

Vector Add Unsigned Doubleword Modulo

vaddudm vD, vA, vB

Adds 2 doublewords modulo 2^64.

Encoding

Binary Layout

4

0:5

vD

6:10

vA

11:15

vB

16:20

192

21:31

 

Format VX-form

Opcode 0x100000C0

Extension VMX (AltiVec)

Operands

• vD
  Target
• vA
  Src A
• vB
  Src B

Example

vaddudm vd, va, vb

Registers Altered

MSR

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Adds each of two unsigned 64-bit doublewords in vA to the corresponding doubleword in vB, with results modulo 2^64 (wrapping on overflow). No status flags are affected; this is a VMX/AltiVec arithmetic operation available on some implementations.

Operation

for i in 0 to 1 do
  vD[i*64:(i+1)*64-1] ← (vA[i*64:(i+1)*64-1] + vB[i*64:(i+1)*64-1]) mod 2^64

Programming Note

This instruction is commonly used for performing element-wise addition of two vectors treating each element as a 64-bit unsigned integer. Ensure that the vector registers are properly aligned and that the VEC bit in the MSR register is set to 1 to avoid exceptions. Be cautious of overflow, as the operation uses modulo arithmetic, which wraps around without generating an exception.