vaddudm

Vector Add Unsigned Doubleword Modulo

vaddudm vD, vA, vB

Adds 2 doublewords modulo 2^64.

Details

The vaddudm instruction performs an unsigned doubleword addition modulo operation on the elements of two vector registers, VRA and VRB, and stores the results in the vector register VRT. Each element is treated as a 64-bit unsigned integer, and the low-order 64 bits of the sum are placed into the corresponding element of VRT.

Pseudocode Operation

if MSR.VEC=0 then Vector_Unavailable()
do i = 0 to 7
   src1 ←EXTZ(VSR[VRA+32].dword[i])
   src2 ←EXTZ(VSR[VRB+32].dword[i])
   VSR[VRT+32].dword[i] ←CHOP64(src1 + src2)
end

Programming Note

This instruction is commonly used for performing element-wise addition of two vectors treating each element as a 64-bit unsigned integer. Ensure that the vector registers are properly aligned and that the VEC bit in the MSR register is set to 1 to avoid exceptions. Be cautious of overflow, as the operation uses modulo arithmetic, which wraps around without generating an exception.

Example

vaddudm vd, va, vb

Encoding

Binary Layout
4
0
vD
6
vA
11
vB
16
192
21
 
Format VX-form
Opcode 0x100000C0
Extension VMX (AltiVec)
Registers Altered MSR

Operands

  • vD
    Target
  • vA
    Src A
  • vB
    Src B