xststdcqp

VSX Scalar Test Data Class Quad-Precision

xststdcqp BF, vB, DCM

Tests the data class of a quad-precision floating-point value and sets condition register bits based on the result.

Details

The xststdcqp instruction tests the data class of the quad-precision floating-point value in VSR[VRB+32] against the specified data classes in DCMX. The results are stored in the condition register CR field BF and FPSCR.FPCC.

Pseudocode Operation

if MSR.VSX=0 then
    VSX_Unavailable()
src ← VSR[VRB+32]
exponent ← src.bit[1:15]
fraction ← src.bit[16:127]
class.NaN ← (exponent = 0x7FFF) & (fraction != 0)
class.Infinity ← (exponent = 0x7FFF) & (fraction = 0)
class.Zero ← (exponent = 0x0000) & (fraction = 0)
class.Denormal ← (exponent = 0x0000) & (fraction != 0)
match ←
    (DCMX.bit[0] & class.NaN) |
    (DCMX.bit[1] & class.Infinity & !sign) |
    (DCMX.bit[2] & class.Infinity & sign) |
    (DCMX.bit[3] & class.Zero & !sign) |
    (DCMX.bit[4] & class.Zero & sign) |
    (DCMX.bit[5] & class.Denormal & !sign) |
    (DCMX.bit[6] & class.Denormal & sign)
CR.bit[4×BF+32] ← FPSCR.FL ← src.sign
CR.bit[4×BF+33] ← FPSCR.FG ← 0b0
CR.bit[4×BF+34] ← FPSCR.FE ← match
CR.bit[4×BF+35] ← FPSCR.FU ← 0b0

Programming Note

The xststdcqp instruction is used to test the data class of a quad-precision floating-point value. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register, otherwise, an exception will be raised. The result is stored in the condition register CR and FPSCR.FPCC, which can be used for conditional branching based on the data class match.

Example

xststdcqp cr0, vb, 0

Encoding

Binary Layout
63
0
BF
1
/
9
DCM
16
vB
706
/
 
Format X-form
Opcode 0xFC000582
Extension VSX
Registers Altered CR, FPSCR

Operands

  • BF
    CR Field
  • vB
    Source
  • DCM
    Mask
  • VRB
    Vector-Scalar Register B
  • DCMX
    Data Class Mask