vsum4ubs

Vector Sum-across Partial (1/4) Unsigned Byte Saturate

vsum4ubs vD, vA, vB

Sums the unsigned byte elements of two vector registers and saturates the result.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

1632

21:31

Format VA-form

Opcode 0x10000608

Extension VMX (AltiVec)

Operands

vD
Target
vA
Src A
vB
Accumulator
VRT
Target Vector Register
VRA
Source Vector Register
VRB
Source Vector Register

Example

vsum4ubs vd, va, vb

Registers Altered

VSCR.SAT

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For vsum4ubs, the sum of the unsigned integer values in the four byte elements contained in each word element of VSR[VRA+32] is added to the unsigned integer value in the corresponding word element of VSR[VRB+32]. If the intermediate result exceeds 2^32 - 1, it saturates to 2^32 - 1 and sets the SAT flag.

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    temp ← EXTZ(VSR[VRB+32].word[i])
    do j = 0 to 3
        temp ← temp + EXTZ(VSR[VRA+32].word[i].byte[j])
    end
    VSR[VRT+32].word[i] ← ui32_CLAMP(temp)
    VSCR.SAT ← sat_flag
end

Programming Note

vsum4ubs is commonly used for accumulating sums of byte elements within vector registers, with saturation to prevent overflow. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation processes four bytes per word, and results are clamped to 32-bit unsigned integers, setting the VSCR.SAT flag if saturation occurs.