vmaxsb

Vector Maximum Signed Byte

vmaxsb vD, vA, vB

Performs a signed byte-wise maximum operation on two vector registers and stores the result in another vector register.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

516

21:31

Format VA-form

Opcode 0x10000102

Extension VMX (AltiVec)

Operands

vD
Target
vA
Src A
vB
Src B
VRT
Target Vector Register
VRA
Source Vector Register
VRB
Source Vector Register

Example

vmaxsb vd, va, vb

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For vmaxsb, each byte element of VSR[VRA+32] is compared with the corresponding byte element of VSR[VRB+32]. The larger value is stored in the corresponding byte element of VSR[VRT+32].

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 15
    src1 ← VSR[VRA+32].byte[i]
    src2 ← VSR[VRB+32].byte[i]
    gt_flag ← EXTS(src1) > EXTS(src2)
    VSR[VRT+32].byte[i] ← gt_flag=1 ? src1 : src2
end

Programming Note

This instruction is used to perform element-wise signed byte comparisons and store the maximum values in the destination vector. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation respects the signed nature of bytes, so developers should be cautious with negative values. This instruction operates on 16 byte elements and does not require any specific alignment for the vector registers.