vmrglh

Vector Merge Low Halfword

vmrglh vD, vA, vB

Interleaves low-order halfwords.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

332

21:31

Format VX-form

Opcode 0x1000014C

Extension VMX (AltiVec)

Operands

vD
Target
vA
Src A
vB
Src B

Example

vmrglh vd, va, vb

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Merges the four low-order (rightmost) halfwords from vA and vB in an alternating interleaved pattern into vD, with vA halfwords in even positions and vB halfwords in odd positions. This VMX instruction does not affect any condition or status registers.

Operation

vD[0:15] ← vA[112:127]
vD[16:31] ← vB[112:127]
vD[32:47] ← vA[96:111]
vD[48:63] ← vB[96:111]
vD[64:79] ← vA[80:95]
vD[80:95] ← vB[80:95]
vD[96:111] ← vA[64:79]
vD[112:127] ← vB[64:79]

Programming Note

The vmrglh instruction is used to merge the lower halfwords from two source vectors into a destination vector. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation interleaves the halfwords from the two sources, so the resulting vector will have elements from both sources in an alternating pattern.