mtvsrwa

Move To VSR Word Algebraic

mtvsrwa XT, RA

Moves the two's-complement integer in bits 32:63 of GPR[RA] to doubleword element 0 of VSR[XT], sign-extended to 64 bits.

Details

The two’s-complement integer in bits 32:63 of GPR[RA] is sign-extended to 64 bits and placed into doubleword element 0 of VSR[XT]. The contents of doubleword element 1 of VSR[XT] are undefined.

Pseudocode Operation

if TX=0 & MSR.FP=0 then FP_Unavailable()
if TX=1 & MSR.VEC=0 then Vector_Unavailable()
VSR[32×TX+T].dword[0] ←EXTS64(GPR[RA].bit[32:63])
VSR[32×TX+T].dword[1] ←0xUUUU_UUUU_UUUU_UUUU

Programming Note

For TX=0, mtvsrwa is treated as a Floating-Point instruction in terms of resource availability. For TX=1, mtvsrwa is treated as a Vector instruction in terms of resource availability.

Extended Mnemonics

Extended Mnemonic Equivalent Instruction
mtfprwa
mtvrwa

Example

mtvsrwa vs1, r4

Encoding

Binary Layout
31
0
XT
6
RA
11
/
16
211
21
TX
31
 
Format XX1-form
Opcode 0x7C0000D3
Extension VSX
Registers Altered MSR

Operands

  • XT
    Target VSR
  • RA
    Source GPR
  • VS
    Target Vector Scalar Register