vspltish

Vector Splat Immediate Signed Halfword

vspltish vD, SIM

Fills vector with immediate 5-bit signed value.

Details

Splats a 5-bit signed immediate value into all 8 halfword elements of vD, sign-extended to 16 bits per halfword. The immediate SIM is a signed 5-bit value (range −16 to 15). No status flags are affected. This is a VMX/AltiVec instruction.

Pseudocode Operation

value ← sign_extend(SIM, 16)
vD ← replicate(value to all 8 halfword positions)

Programming Note

The vspltish instruction is used to replicate a signed halfword value across all elements of a vector register. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The immediate value is sign-extended to 16 bits and then replicated in each halfword element of the target vector register.

Example

vspltish vd, 4

Encoding

Binary Layout
4
0
vD
6
SIM
11
00000
16
844
21
 
Format VX-form
Opcode 0x1000034C
Extension VMX (AltiVec)
Registers Altered MSR

Operands

  • vD
    Target
  • SIM
    Immediate