vspltish

Vector Splat Immediate Signed Halfword

vspltish vD, SIM

Fills vector with immediate 5-bit signed value.

Details

The vspltish instruction splats an immediate signed halfword value across all elements of a vector register. It sign-extends the SIM field to 16 bits and replicates this value in each halfword element of the target vector register.

Pseudocode Operation

if MSR.VEC=0 then Vector_Unavailable()
do i = 0 to 7
   VSR[VRT+32].hword[i] ←EXTS16(SIM, 16)
end

Programming Note

The vspltish instruction is used to replicate a signed halfword value across all elements of a vector register. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The immediate value is sign-extended to 16 bits and then replicated in each halfword element of the target vector register.

Example

vspltish vd, 4

Encoding

Binary Layout
4
0
vD
6
SIM
11
00000
16
844
21
 
Format VX-form
Opcode 0x1000034C
Extension VMX (AltiVec)
Registers Altered MSR

Operands

  • vD
    Target
  • SIM
    Immediate