ddivq

Decimal Divide Quad-Precision

ddivq vD, vA, vB

Divides two 128-bit DFP numbers.

Encoding

Binary Layout

63

0:5

vD

6:10

vA

11:15

vB

16:20

546

21:30

/

31

 

Format X-form

Opcode 0xFC000444

Extension Decimal Floating-Point

Operands

• vD
  Target
• vA
  Src A
• vB
  Src B

Example

ddivq vd, va, vb

Registers Altered

FPSCR

Related

More in Decimal Floating-Point

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Divides the 128-bit Decimal Floating-Point value in vA by the value in vB, storing the result in vD. The operation follows DFP semantics, respecting the current rounding mode in FPSCR. Division by zero signals the ZX exception, and inexact results are rounded according to FPSCR[RN]. The FPSCR is updated with exception flags.

Operation

vD ← vA ÷ vB (DFP arithmetic)
FPSCR ← updated with exception flags (XX, ZX, UX, OX, IE)

Programming Note

The ddivq instruction is used for performing decimal division with quad-precision operands. Ensure that the operands are correctly aligned and formatted to avoid precision loss. The result rounding mode is controlled by the DRN field in the FPSCR register, so verify this setting before execution. This instruction operates at a privilege level that allows access to floating-point registers and may raise exceptions if operands are invalid or division by zero occurs.