divdu

Divide Doubleword Unsigned

divdu RT, RA, RB

Divides the 64-bit value in RA by the 64-bit value in RB (Unsigned).

Details

Divides the full 64-bit value in RA (treated as unsigned) by the full 64-bit value in RB (treated as unsigned) and places the 64-bit quotient in RT. If RB is zero, RT is undefined and no exception is raised. When Rc=1, CR0 is updated based on the result; OE is reserved and must be 0.

Pseudocode Operation

dividend ← (RA)
divisor ← (RB)
if divisor = 0 then
  quotient ← undefined
else
  quotient ← dividend ÷ divisor
RT ← quotient
if Rc = 1 then
  CR0 ← (quotient = 0) || (quotient < 0) || (quotient > 0) || SO

Programming Note

When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.

Example

divdu r3, r4, r5

// r3 = r4 / r5 (64-bit Unsigned).

Encoding

Binary Layout
31
0
RT
6
RA
11
RB
16
OE
21
457
22
Rc
31
 
Format XO-form
Opcode 0x7C000392
Extension Base
Registers Altered CR0

Operands

  • RT
    Target Register (Quotient)
  • RA
    Dividend
  • RB
    Divisor