divdu

Divide Doubleword Unsigned

divdu RT, RA, RB

Divides the 64-bit value in RA by the 64-bit value in RB (Unsigned).

Details

The divdu instruction performs an unsigned division of a 64-bit dividend by a 64-bit divisor. The quotient is placed into the target register RT, and the remainder is discarded. Both operands are treated as unsigned integers.

Pseudocode Operation

RT <- (RA) /u (RB)

Programming Note

When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.

Example

divdu r3, r4, r5

Encoding

Binary Layout
31
0
RT
6
RA
11
RB
16
OE
21
457
22
Rc
31
 
Format XO-form
Opcode 0x7C000392
Extension Base
Registers Altered CR0

Operands

  • RT
    Target Register (Quotient)
  • RA
    Dividend
  • RB
    Divisor