vcipher

Vector Cipher (AES)

vcipher vD, vA, vB

Performs one round of AES encryption (SubBytes, ShiftRows, MixColumns, AddRoundKey).

Encoding

Binary Layout

0:5

6:10

11:15

16:20

1288

21:31

Format VX-form

Opcode 0x10000508

Extension Vector Crypto

Operands

vD
Target State
vA
Current State
vB
Round Key
VRT
Target Vector Register
VRA
Source Vector Register containing the intermediate state array
VRB
Source Vector Register containing the round key

Example

vcipher v1, v2, v3

// Hardware AES Encrypt.

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The instruction performs one round of the AES cipher operation on the intermediate State array, sequentially applying the transforms SubBytes(), ShiftRows(), MixColumns(), and AddRoundKey() as defined in FIPS-197. The result is placed into VSR[VRT+32], representing the new intermediate state of the cipher operation.

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
State ←VSR[VRA+32]
RoundKey ←VSR[VRB+32]
vtemp1 ←SubBytes(State)
vtemp2 ←ShiftRows(vtemp1)
vtemp3 ←MixColumns(vtemp2)
VSR[VRT+32] ←vtemp3 ⊕ RoundKey

Programming Note

The vcipher instruction performs a single AES cipher round, requiring the Vector Facility to be enabled. Ensure that the VRA and VRB registers point to the correct intermediate state and round key in vector storage registers. The result is stored in VSR[VRT+32]. This instruction operates at the user privilege level and will raise an exception if the Vector Facility is not available.