vmulesd

Vector Multiply Even Signed Doubleword

vmulesd VRT,VRA,VRB

Multiplies the even doublewords of two vector registers and places the result in another vector register.

Details

The instruction multiplies the signed integer values in the even doublewords of VSR[VRA+32] and VSR[VRB+32], and stores the 128-bit product in VSR[VRT+32].

Pseudocode Operation

if MSR.VEC=0 then
    Vector_Unavailable()
src1 ←EXTS(VSR[VRA+32].dword[0])
src2 ←EXTS(VSR[VRB+32].dword[0])
VSR[VRT+32] ←CHOP128(src1 × src2)

Programming Note

This instruction is used for multiplying signed integers in the even doublewords of two vector registers and storing the 128-bit product. Ensure that the Vector Facility (MSR.VEC) is enabled; otherwise, a Vector_Unavailable exception will be raised. The operation is performed on the first doubleword of each input register, and the result is truncated to 128 bits before being stored in the destination register.

Example

vmulesd v1, v2, v3

Encoding

Binary Layout
4
0
VRT
6
VRA
11
VRB
16
 
Format VX-form
Opcode 0x100003C8
Extension VMX (AltiVec)
Registers Altered MSR

Operands

  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Source Vector Register