vrlw

Vector Rotate Left Word

vrlw vD, vA, vB

Rotates each word element of the source vector left by a specified number of bits.

Details

For vrlw, each word element in VSR[VRA+32] is rotated left by the number of bits specified in the low-order 5 bits of the corresponding word element in VSR[VRB+32]. The result is placed into the corresponding word element in VSR[VRT+32].

Pseudocode Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    src1 ← VSR[VRA+32].word[i]
    sh ← VSR[VRB+32].word[i].bit[27:31]
    VSR[VRT+32].word[i] ← src1 <<< sh

Programming Note

The vrlw instruction is commonly used for performing bitwise rotations on vector elements. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set to 1; otherwise, a Vector_Unavailable exception will be raised. The shift amount is determined by the low-order 5 bits of each word element in the second source vector register (VRB). Be cautious with alignment as unaligned access can lead to performance penalties or exceptions depending on the system configuration.

Example

vrlw vd, va, vb

Encoding

Binary Layout
4
0
VRT
6
VRA
11
VRB
16
132
21
 
Format VX-form
Opcode 0x10000084
Extension VMX (AltiVec)
Registers Altered MSR

Operands

  • vD
    Target
  • vA
    Data
  • vB
    Rotate Count
  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Source Vector Register