vadduqm

Vector Add Unsigned Quadword Modulo

vadduqm vD, vA, vB

Adds the contents of two vector registers and updates the destination register with the result modulo 2^128.

Encoding

Binary Layout

4

0:5

vD

6:10

vA

11:15

vB

16:20

256

21:31

 

Format VA-form

Opcode 0x10000100

Extension VMX (AltiVec)

Operands

• vD
  Target
• vA
  Src A
• vB
  Src B
• VRT
  Target Vector Register
• VRA
  Source Vector Register
• VRB
  Source Vector Register

Example

vadduqm vd, va, vb

Registers Altered

MSR

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For vadduqm, the sum of the contents of vector registers VRA and VRB is placed into vector register VRT. The operation is performed modulo 2^128.

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
src1 ←EXTZ(VSR[VRA+32])
src2 ←EXTZ(VSR[VRB+32])
VSR[VRT+32] ←CHOP128(src1 + src2)

Programming Note

This instruction is used for adding two 128-bit unsigned integers stored in vector registers modulo 2^128. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set to 1; otherwise, a Vector_Unavailable exception will be raised. The operation does not require any specific alignment for the data being processed.