xscvsxddp

VSX Scalar Convert with round Signed Doubleword to Double-Precision format

xscvsxddp XT,RB

Converts a signed doubleword integer from VSX register XB to a double-precision floating-point number in VSX register XT, rounding according to the FPSCR.RN setting.

Details

The instruction converts the signed integer value in doubleword element 0 of VSR[XB] to an unbounded-precision floating-point value and rounds it to double-precision format using the rounding mode specified by RN. The result is placed into doubleword element 0 of VSR[XT], with doubleword element 1 set to zero.

Pseudocode Operation

if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src ← bfp_CONVERT_FROM_SI64(VSR[32×BX+B].dword[0])
rnd ← bfp_ROUND_TO_BFP64(0b0, FPSCR.RN, v)
result ← bfp64_CONVERT_FROM_BFP(rnd)
if xx_flag=1 then SetFX(FPSCR.XX)
VSR[32×TX+T].dword[0] ← result
VSR[32×TX+T].dword[1] ← 0x0000_0000_0000_0000
FPSCR.FPRF ← fprf_CLASS_BFP64(result)
FPSCR.FR ← inc_flag
FPSCR.FI ← xx_flag

Programming Note

Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.

Example

xscvsxddp vs1, r5

Encoding

Binary Layout
60
0
XT
6
/
11
XB
16
752
21
 
Format X-form
Opcode 0xF00002F0
Extension VSX
Registers Altered XX, FPRF

Operands

  • XT
    Target Vector-Scalar Register
  • RB
    Source Vector-Scalar Register
  • XB
    Source VSX Register