xssqrtsp

VSX Scalar Square Root Single-Precision

xssqrtsp XT,XB

Computes the square root of a single-precision floating-point number in VSX.

Details

The unbounded-precision square root of src is produced. The intermediate result is rounded to single-precision using the rounding mode specified by RN. The result is placed into doubleword element 0 of VSR[XT] in double-precision format. The contents of doubleword element 1 of VSR[XT] are set to 0.

Pseudocode Operation

if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[0])
v ←bfp_SQUARE_ROOT(src)
rnd ←bfp_ROUND_TO_BFP32(FPSCR.RN,v)
result32 ←bfp32_CONVERT_FROM_BFP(rnd)
result64 ←bfp64_CONVERT_FROM_BFP(rnd)
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if vxsqrt_flag=1 then SetFX(FPSCR.VXSQRT)
if ox_flag=1 then SetFX(FPSCR.OX)
if ux_flag=1 then SetFX(FPSCR.UX)
if xx_flag=1 then SetFX(FPSCR.XX)
vx_flag ←vxsnan_flag | vxsqrt_flag
vex_flag ←FPSCR.VE & vx_flag
if vex_flag=0 then do
    VSR[32×TX+T].dword[1] ←0x0000_0000_0000_0000
    FPSCR.FPRF ←fprf_CLASS_BFP32(result32)
    FPSCR.FR  ←inc_flag
    FPSCR.FI  ←xx_flag
end else do
    FPSCR.FR  ←0b0
    FPSCR.FI  ←0b0
end

Programming Note

Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.

Example

xssqrtsp vs1, vs3

Encoding

Binary Layout
1111
0
0001
6
0000
11
0000
16
0000
21
0000
30 31
0000
1000
 
Format XX2-form
Opcode 0xF000002C
Extension VSX
Registers Altered FPSCR, VSR[XT], FPRF, FR, FI, FX, OX, UX, VXSNAN, VXSQRT

Operands

  • XT
    Target Vector-Specific Register
  • XB
    Source Vector-Specific Register
  • VX
    Target Vector Register
  • VB
    Source Vector Register