xvmulsp

VSX Vector Multiply Single-Precision

xvmulsp XT, XA, XB

Multiplies the contents of two single-precision floating-point values and places the result into a vector register.

Encoding

Binary Layout

60

0:5

XT

6:10

XA

11:15

XB

16:20

80

21:31

 

Format XX3-form

Opcode 0xF0000280

Extension VSX

Operands

• XT
  Target
• XA
  Src A
• XB
  Src B

Example

xvmulsp vs1, vs2, vs3

Registers Altered

FPSCR

Related

More in VSX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

VSX Vector Multiply Single-Precision multiplies four single-precision floating-point elements from VSX registers XA and XB, storing the results in VSX register XT. This VSX category instruction processes four 32-bit elements in parallel and may update FPSCR with floating-point exception flags.

Operation

XT[0:31] ← XA[0:31] × XB[0:31]
XT[32:63] ← XA[32:63] × XB[32:63]
XT[64:95] ← XA[64:95] × XB[64:95]
XT[96:127] ← XA[96:127] × XB[96:127]

Programming Note

The xvmulsp instruction performs element-wise multiplication of single-precision floating-point values in vector registers. Ensure that the input vectors are properly aligned to avoid alignment faults. Be cautious with NaN and infinity handling, as they follow specific rules for propagation and sign determination. This instruction operates at user privilege level.