xvmsubmdp

VSX Vector Multiply-Subtract Type-M Double-Precision

xvmsubmdp VRT, VRA, VRB, VRC

Multiplies corresponding double-precision floating-point elements of two VSX registers, subtracts the corresponding element of a third register, and stores the results, using the Type-M (multiplicand) form.

Encoding

Binary Layout

111100

0:5

VRT

6:10

VRA

11:15

VRB

16:20

01111

21:30

001

Format XX3-form

Opcode 0xF00003C8

Extension VSX

Operands

VRT
Target Vector Register
VRA
Source Vector Register
VRB
Source Vector Register
VRC
Source Vector Register

Example

xvmsubmdp v1, v2, v3, v4

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For each of the two double-precision floating-point elements, the instruction multiplies the corresponding elements of VRA and VRT, subtracts the corresponding element of VRB, and places the result into the corresponding element of VRT. This is the Type-M variant, meaning VRT serves as both a source (multiplicand) and the destination register. The operation computes VRT ← (VRA × VRT) - VRB for each element.

Operation

do i = 0 to 1
  VRT.fpr[i] ← RND(VRA.fpr[i] × VRT.fpr[i] - VRB.fpr[i])
end

Programming Note

This instruction is commonly used in applications requiring complex floating-point arithmetic operations, such as scientific computations and graphics processing. Ensure that the input registers (VRA, VRT, VRB) are properly aligned to avoid performance penalties or exceptions. The Type-M variant requires careful handling since VRT is both a source and destination register, which can lead to unexpected results if not managed correctly. This instruction operates at user privilege level but may raise exceptions for invalid operations like division by zero or overflow.