xvrdpic

VSX Vector Round to Double-Precision Integer

xvrdpic XT,XB

Rounds each double-precision floating-point element of a vector to an integer using the current rounding mode.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

21:31

Format XX2-form

Opcode 0xF00003AC

Extension VSX

Operands

XT
Target Vector-Specific Register
XB
Source Vector-Specific Register

Example

xvrdpic vs1, vs3

Registers Altered

FPSCR, VXSNAN, XX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For xvrdpic, each double-precision floating-point element in VSR[XB] is rounded to an integer using the rounding mode specified by FPSCR.RN. The result is placed into VSR[XT]. If any element results in a Signalling NaN, it is converted to a Quiet NaN and VXSNAN is set.

Operation

if MSR.VSX=0 then VSX_Unavailable()

ex_flag ←0b0
do i = 0 to 1
    reset_xflags()
    src ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[i])
    if FPSCR.RN=0b00 then rnd ←bfp_ROUND_TO_INTEGER(0b000, src)
    if FPSCR.RN=0b01 then rnd ←bfp_ROUND_TO_INTEGER(0b001, src)
    if FPSCR.RN=0b10 then rnd ←bfp_ROUND_TO_INTEGER(0b010, src)
    if FPSCR.RN=0b11 then rnd ←bfp_ROUND_TO_INTEGER(0b011, src)

    vresult.dword[i] ←bfp64_CONVERT_FROM_BFP(rnd)

    if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
    if xx_flag=1 then SetFX(FPSCR.XX)

    ex_flag ←ex_flag | (FPSCR.VE & vxsnan_flag)
    ex_flag ←ex_flag | (FPSCR.XE & xx_flag)
end

if ex_flag=0 then VSR[32×TX+T] ←vresult

Programming Note

This instruction rounds each double-precision floating-point element in the source vector to an integer using the rounding mode specified by FPSCR.RN. Ensure that VSX is enabled; otherwise, a VSX_Unavailable exception will occur. Be cautious of NaN values, as they are converted to Quiet NaNs and VXSNAN is set. The instruction respects the rounding modes defined in FPSCR.RN, so ensure this register is correctly configured for your needs.