vmsumshs

Vector Multiply-Sum Signed Halfword Saturate

vmsumshs vD, vA, vB, vC

Performs a vector multiply-sum operation on signed halfwords and saturates the result.

Details

For vmsumshs, each element in VRA and VRB is multiplied by corresponding elements in VRC. The results are summed and saturated if necessary.

Pseudocode Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    temp ←EXTS(VSR[VRC+32].word[i])
    do j = 0 to 1
        src1 ←EXTS(VSR[VRA+32].word[i].hword[j])
        src2 ←EXTS(VSR[VRB+32].word[i].hword[j])
        temp ←temp + (src1 × src2)
    end
    VSR[VRT+32].word[i] ←si32_CLAMP(temp)
    VSCR.SAT ←sat_flag
end

Programming Note

vmsumshs is used for vectorized operations involving signed halfword multiplication and summation. Ensure that the Vector Status and Control Register (VSCR) is properly managed, especially when handling saturation flags. This instruction operates at the user privilege level and will raise an exception if the vector facility is not enabled in the Machine State Register (MSR).

Example

vmsumshs vd, va, vb, vc

Encoding

Binary Layout
4
0
vD
6
vA
11
vB
16
vC
21
41
 
Format VA-form
Opcode 0x10000029
Extension VMX (AltiVec)
Registers Altered VSCR

Operands

  • vD
    Target
  • vA
    Src A
  • vB
    Src B
  • vC
    Accumulator
  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Source Vector Register
  • VRC
    Source Vector Register