vclzw

Vector Count Leading Zeros Word

vclzw vD, vB

Counts the number of leading zero bits in each word element of a vector register.

Encoding

Binary Layout

4

0:5

vD

6:10

0

11:15

vB

16:20

1922

21:31

 

Format VX-form

Opcode 0x10000782

Extension VMX (AltiVec)

Operands

• vD
  Target
• vB
  Source
• VRT
  Target Vector Register
• VRB
  Source Vector Register

Example

vclzw vd, vb

Registers Altered

MSR

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For vclzw, the number of consecutive zero bits starting at bit 0 of each word element in VSR[VRB+32] is counted and placed into the corresponding word element in VSR[VRT+32].

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    n ←0
do while n < 32
    if VSR[VRB+32].word[i].bit[n] = 0b1 then
        leave
    n ←n + 1
end
VSR[VRT+32].word[i] ←n
end

Programming Note

vclzw counts leading zeros in each word of the input vector. Ensure VSR[VRB+32] is properly aligned and accessible. This instruction operates at user privilege level unless MSR.VEC is set, in which case it raises an exception.