vcmpgtsq

Vector Compare Greater Than Signed Quadword

vcmpgtsq VRT,VRA,VRB

Compares two signed quadwords and sets the result based on whether the first is greater than the second.

Encoding

Binary Layout

0:5

VRT

6:10

VRA

11:15

VRB

16:20

21:31

Format VC-form

Opcode 0x10000387

Extension VMX (AltiVec)

Operands

VRT
Target Vector Register
VRA
Source Vector Register
VRB
Source Vector Register

Example

vcmpgtsq v1, v2, v3

Registers Altered

CR6 (if Rc=1)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For vcmpgtsq, the contents of VSR[VRA+32] (src1) are compared to the contents of VSR[VRB+32] (src2). If src1 > src2, VSR[VRT+32] is set to all 1s; otherwise, it is set to all 0s. If Rc=1, CR field 6 is updated.

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
all_true ←1
all_false ←1
src1 ←EXTS(VSR[VRA+32])
src2 ←EXTS(VSR[VRB+32])
if src1 > src2 then do
    VSR[VRT+32] ← 0xFFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF
    all_false ←0
end else do
    VSR[VRT+32] ← 0x0000_0000_0000_0000_0000_0000_0000_0000
    all_true ←0
end
if Rc=1 then
    CR.field[6] ←all_true || 0b0 || all_false || 0b0

Programming Note

When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.