vctzh

Vector Count Trailing Zeros Halfword

vctzh vD, vB

Counts trailing zeros in each halfword.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

1858

21:31

Format VX-form

Opcode 0x101D0602

Extension VMX (AltiVec)

Operands

vD
Target
vB
Source

Example

vctzh vd, vb

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Counts the number of trailing zero bits in each of the 8 halfword elements in vB and stores the result in the corresponding halfword of vD. Each result is an unsigned integer in the range 0-16. No status flags are affected. This instruction is part of the VMX (AltiVec) extension.

Operation

for i in 0 to 7 do
  count ← 0
  halfword ← vB[i*16 : i*16+15]
  if halfword = 0 then
    count ← 16
  else
    for j in 0 to 15 do
      if halfword[j] = 1 then
        break
      count ← count + 1
  vD[i*16 : i*16+15] ← count

Programming Note

The vctzh instruction is useful for counting trailing zeros in each halfword of a vector, which can be helpful in bit manipulation and data compression tasks. Ensure that the Vector Facility (VEC) is enabled in the MSR register to avoid a Vector_Unavailable exception. The instruction processes 8 halfwords per vector register, so ensure your data is properly aligned and structured for optimal performance.