vextdubvlx

Vector Extract Double Unsigned Byte to VSR Using GPR-specified Left-Index VA-form

vextdubvlx VRT,VRA,VRB,RC

Extracts a double unsigned byte from two vector registers using a left-index specified by a general-purpose register and places it into another vector register.

Encoding

Binary Layout

0:5

VRT

6:10

VRA

11:15

VRB

16:20

21:31

Format VA-form

Opcode 0x10000018

Extension VMX (AltiVec)

Operands

VRT
Target Vector Register
VRA
Source Vector Register
VRB
Source Vector Register
RC
General Purpose Register containing the index
VD
Destination Vector Register
VS
Source Vector Register
VSRA
Index Source Vector Register

Example

vextdubvlx v1, v2, v3, r6

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The instruction extracts a double unsigned byte from the concatenation of two vector registers (VRA+32 and VRB+32) based on an index derived from bits 59:63 of GPR[RC]. The extracted byte is zero-extended and placed into the first doubleword of VSR[VRT+32], while the second doubleword is set to zero.

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
index ← GPR[RC].bit[59:63]
vsrc.qword[0] ← VSR[VRA+32]
vsrc.qword[1] ← VSR[VRB+32]
VSR[VRT+32].dword[0] ← EXTZ64(vsrc.byte[index])
VSR[VRT+32].dword[1] ← 0x0000_0000_0000_0000

Programming Note

This instruction is useful for extracting a specific byte from two concatenated vector registers and placing it into the first doubleword of another VSR, with the second doubleword zeroed. Ensure that the index derived from GPR[RC] bits 59:63 is within bounds to avoid undefined behavior. The instruction requires the Vector Facility to be enabled; otherwise, a Vector_Unavailable exception will be raised.