psq_st

Paired Single Quantized Store

psq_st FRS, D(RA), W, I

Stores a paired single to memory (Embedded/Legacy).

Encoding

Binary Layout

60

0:5

FRS

6:10

RA

11:15

W

16:20

I

21:30

7

31

 

Format X-form

Opcode 0xF0000007

Extension VMX (AltiVec)

Operands

• FRS
  Source
• D
  Disp
• RA
  Base
• W
  Width
• I
  Scale

Example

psq_st f1, 0(r4), 0, 0

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Stores a pair of single-precision floating-point values from an FPR to memory, with optional quantization/scaling applied. The W field controls element width, and the I field specifies the scale factor applied during store. This is a legacy VMX/AltiVec instruction primarily found on embedded PowerPC implementations.

Operation

EA ← (RA = 0 ? 0 : GPR[RA]) + D
data ← quantize(FPR[FRS], width W, scale I)
[EA] ← data