lfsu

Load Floating-Point Single with Update Indexed

lfsu FRT,D(RA)

Loads a floating-point single-precision operand from memory into a register and updates the base address.

Details

The word in storage addressed by EA is interpreted as a floating-point single-precision operand. This word is converted to floating-point double format (see page 149) and placed into register FRT. The effective address (EA) is the sum of RA and D, and EA is placed into register RA.

Pseudocode Operation

EA ← (RA) + EXTS(D)
FRT ← DOUBLE(MEM(EA, 4))
RA ← EA
if RA=0 then
    the instruction form is invalid

Programming Note

The base register (RA) is updated with the effective address after the memory access. RA must not be 0 and must differ from the destination register; violating this constraint produces undefined results.

Example

lfsu f1, 0(r4)

Encoding

Binary Layout
0
0
FRT
6
RA
11
D
16
 
Format X-form
Opcode 0xC4000000
Extension Floating-Point
Registers Altered FPSCR

Operands

  • FRT
    Target Floating-Point Register
  • RA
    Base General Purpose Register
  • D
    Displacement