xssubqpo

VSX Scalar Subtract Quad-Precision Odd

xssubqpo VRT,VRA,VRB

Used for Quad-Precision arithmetic on hardware that splits quads.

Encoding

Binary Layout
63
0:5
FRT
6:10
FRA
11:15
FRB
16:20
514
21:30
Rc
31
 
Format X-form
Opcode 0xFC000408
Extension VSX

Operands

  • vD
    Target
  • vA
    Src A
  • vB
    Src B
  • VRT
    Target Vector-Scalar Register
  • VRA
    Source Vector-Scalar Register
  • VRB
    Source Vector-Scalar Register

Example

xssubqpo vd, va, vb

Registers Altered

FPSCR

Related

More in VSX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Subtracts the odd (high-order) portion of a 128-bit quad-precision floating-point value in VSR vB from the odd portion in VSR vA, placing the result in VSR vD. This instruction is used on systems that split quad-precision operands into even/odd register pairs. FPSCR exception flags are updated based on the operation result. Requires VSX support.

Operation

vD ← (vA - vB) as quad-precision (odd portion operation)
FPSCR[XX,ZX,OX,UX,VXISI] ← updated based on operation result

Programming Note

This instruction is commonly used for precise floating-point arithmetic operations in scientific computing. Be cautious of NaN handling; if src2 is a Quiet NaN, it will propagate as the result without performing any subtraction. Ensure that inputs are properly aligned to avoid alignment faults. This operation requires FPSCR for exception flags and rounding modes.