xvxsigdp

Vector Extract Significand Double-Precision

xvxsigdp XT,XB

Extracts the significand of double-precision floating-point values from a vector register and places them into another vector register.

Details

For xvxsigdp, the significand of each double-precision floating-point value in the source vector register VSR[XB] is extracted and placed into the target vector register VSR[XT].

Pseudocode Operation

if MSR.VSX=0 then VSX_Unavailable()
do i = 0 to 1
    src ←VSR[32×BX+B].dword[i]
    exponent ←EXTZ(src.bit[1:11])
    fraction ←EXTZ64(src.bit[12:63])
    if (exponent != 0) & (exponent != 2047) then
        fraction ←fraction | (0x001 || 520)
    VSR[32×TX+T].dword[i] ←fraction
end

Programming Note

This instruction extracts the significand from each double-precision floating-point value in the source vector register and places it into the target vector register. Ensure that the VSX (Vector Scalar Extensions) is enabled, as attempting to use this instruction when VSX is unavailable will result in an exception. The operation does not modify the exponent or sign bit of the original values.

Example

xvxsigdp vs1, vs3

Encoding

Binary Layout
T
0
1
6
B
11
475
16
BX
21
TX
30 31
 
Format XX2-form
Opcode 0xF001076C
Extension VSX

Operands

  • XT
    Target Vector Register
  • XB
    Source Vector Register
  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Source Vector Register