vncipher

Vector Inverse Cipher (AES)

vncipher vD, vA, vB

Performs one round of an AES inverse cipher operation on the intermediate state array.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

1352

21:31

Format VX-form

Opcode 0x10000548

Extension Vector Crypto

Operands

vD
Target State
vA
Current State
vB
Round Key
VRT
Target Vector Register
VRA
Source Vector Register containing the intermediate state array
VRB
Source Vector Register containing the round key

Example

vncipher v1, v2, v3

// Hardware AES Decrypt.

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The instruction performs one round of an AES inverse cipher operation, sequentially applying the transforms InvShiftRows(), InvSubBytes(), AddRoundKey(), and InvMixColumns() to the intermediate State array.

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
State ← VSR[VRA+32]
RoundKey ← VSR[VRB+32]
vtemp1 ← InvShiftRows(State)
vtemp2 ← InvSubBytes(vtemp1)
vtemp3 ← vtemp2 ⊕ RoundKey
VSR[VRT+32] ← InvMixColumns(vtemp3)

Programming Note

This instruction is used to perform a single round of the AES inverse cipher, which includes operations like InvShiftRows, InvSubBytes, AddRoundKey, and InvMixColumns. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The input state and round key must be correctly loaded into the appropriate vector registers (VRA+32 and VRB+32), respectively, and the result will be stored in VRT+32. This operation is typically used in cryptographic algorithms that require AES decryption.