tlbiel

TLB Invalidate Entry Local

tlbiel RS, RIC, PRS, effR

Invalidates a TLB entry on the current processor only.

Details

The tlbiel instruction invalidates a Translation Lookaside Buffer (TLB) entry locally. The operation is determined by the values in the RB, RS, RIC, PRS, and R fields.

Pseudocode Operation

case (RIC):
  case (0b00):
    if RIC=0 | RIC=2 then
      for each partition-scoped TLB entry for each thread
        if entry_LPID=search_LPID
          then TLB entry ←invalid
    if RIC=1 | RIC=2 then
      for each thread
        invalidate partition-scoped page walk caching associated with partition search_LPID
    if RIC=2 then
      for each thread
        invalidate Partition Table caching associated with partition search_LPID
  case (0b01):
    if RIC=0 | RIC=2 then
      if PRS=0 & ((MSRHV=1) | (effR=0)) then
        for each partition-scoped TLB entry for each thread
          if entry_LPID=search_LPID
            then TLB entry ←invalid
      if PRS=1 then
        for each process-scoped TLB entry for each thread
          if entry_LPID=search_LPID
            then TLB entry ←invalid
    if RIC=1 | RIC=2 then
      for each thread
        if (PRS=0)&(MSRHV=1) then
          invalidate partition-scoped page walk caching associated with partition search_LPID
        if PRS=1 then
          invalidate process-scoped page walk caching associated with partition search_LPID
    if RIC=2 then
      if (PRS=0)&(MSRHV=1) then
        invalidate Partition Table caching associated with partition search_LPID
      if PRS=1 then
        invalidate Process Table caching associated with partition search_LPID
  case (0b10):
    if RIC=0 | RIC=2 then
      if (PRS=0)&((MSRHV=1) | (effR=0)) then
        for each partition-scoped TLB entry for each thread
          if entry_LPID=search_LPID
            then TLB entry ←invalid
      if PRS=1 then
        for each process-scoped TLB entry for each thread
          if entry_LPID=search_LPID
            then TLB entry ←invalid
    if RIC=1 | RIC=2 then
      for each thread
        if (PRS=0)&(MSRHV=1) then
          invalidate partition-scoped page walk caching associated with partition search_LPID
        if PRS=1 then
          invalidate process-scoped page walk caching associated with partition search_LPID
    if RIC=2 then
      if (PRS=0)&(MSRHV=1) then
        invalidate Partition Table caching associated with partition search_LPID
      if PRS=1 then
        invalidate Process Table caching associated with partition search_LPID
  case (0b11):
    if RIC=0 | RIC=2 then
      if MSRHV=1 then
        for all threads
          if PRS=0 then
            all partition-scoped TLB entries ←invalid
          else
            all process-scoped TLB entries ←invalid
      if (MSRHV=0) & (PRS=1) then
        for each process-scoped TLB entry for each thread
          if TLBELPID=search_LPID
            then TLB entry ←invalid
      if (MSRHV=0) & (PRS=0) & (effR=0) then
        for each partition-scoped TLB entry for each thread
          if TLBELPID=search_LPID
            then TLB entry ←invalid
    if RIC=1 | RIC=2 then
      if MSRHV=1 then
        if PRS=0 then
          for all threads
            invalidate all partition-scoped page walk caching
        else
          for all threads
            invalidate all process-scoped page walk caching
      if (MSRHV=0) & (PRS=1) then
        for each thread
          invalidate process-scoped page walk caching associated with partition search_LPID
    if RIC=2 then
      if MSRHV=1 then
        if PRS=0 then
          for each thread
            invalidate all Partition Table caching
        else
          for each thread
            invalidate all Process Table caching
      if (MSRHV=0) & (PRS=1) then

Programming Note

The tlbiel instruction is used to locally invalidate Translation Lookaside Buffer (TLB) entries based on various criteria specified by the RB, RS, RIC, PRS, and R fields. It is important to ensure that the correct values are set in these fields to achieve the desired TLB invalidation. This instruction operates at a privilege level that requires supervisor or higher authority, and it should be used carefully to avoid unintended side effects on system performance.

Example

tlbiel r3, 0, 0, effr

Encoding

Binary Layout
0
0
RS
6
RIC
10
PRS
11
R
12
RB
 
Format X-form
Opcode 0x7C000224
Extension Privileged
Registers Altered MSR

Operands

  • RB
    Addr
  • RS
    Source General Purpose Register containing the LPID or PID
  • RIC
    Radix Invalidate Control bits
  • PRS
    Partition Scope bit
  • effR
    Effective Radix bit
  • R
    Effective Register bit, indicates if the operation affects effective registers