tlbiel

TLB Invalidate Entry Local

tlbiel RS, RIC, PRS, effR

Invalidates a TLB entry on the current processor only.

Details

Invalidates a TLB entry on the current processor without affecting other processors. The operation is controlled by RIC (Radix Invalidate Control), PRS (Partition Scope), and R (Effective Radix) bits; RS contains the LPID or PID, and RB provides the address to invalidate. This is a privileged instruction requiring Hypervisor mode.

Pseudocode Operation

// Invalidate TLB entry based on address, LPID/PID, and control fields
if R = 0 then
  // Page Table (PT) invalidation
  tlb_invalidate_pt(RB, RS, PRS, RIC)
else
  // Radix Table (RT) invalidation
  tlb_invalidate_rt(RB, RS, PRS, RIC)

Programming Note

The tlbiel instruction is used to locally invalidate Translation Lookaside Buffer (TLB) entries based on various criteria specified by the RB, RS, RIC, PRS, and R fields. It is important to ensure that the correct values are set in these fields to achieve the desired TLB invalidation. This instruction operates at a privilege level that requires supervisor or higher authority, and it should be used carefully to avoid unintended side effects on system performance.

Example

tlbiel r3, 0, 0, effr

Encoding

Binary Layout
0
0
RS
6
RIC
10
PRS
11
R
12
RB
 
Format X-form
Opcode 0x7C000224
Extension Privileged
Registers Altered MSR

Operands

  • RB
    Addr
  • RS
    Source General Purpose Register containing the LPID or PID
  • RIC
    Radix Invalidate Control bits
  • PRS
    Partition Scope bit
  • effR
    Effective Radix bit
  • R
    Effective Register bit, indicates if the operation affects effective registers