daddq
Decimal Add Quad-Precision
Adds two 128-bit DFP numbers.
Details
Adds two 128-bit Decimal Floating-Point (DFP) values held in vA and vB, storing the result in vD. The operation follows DFP semantics, respecting the current rounding mode in FPSCR and producing an exact result or DFP overflow/underflow exception as appropriate. The FPSCR is updated with exception flags.
Pseudocode Operation
vD ← vA + vB (DFP arithmetic)
FPSCR ← updated with exception flags (XX, ZX, UX, OX, IE)
Programming Note
The daddq instruction is used for adding two quad-precision decimal numbers. Ensure that the operands are correctly aligned to avoid precision errors. Be aware of potential overflow conditions, which will be indicated in the FPSCR register. This operation requires floating-point privilege level access.
Example
Encoding
Operands
-
vD
Target -
vA
Src A -
vB
Src B