daddq

Decimal Add Quad-Precision

daddq vD, vA, vB

Adds two 128-bit DFP numbers.

Encoding

Binary Layout

63

0:5

vD

6:10

vA

11:15

vB

16:20

2

21:30

/

31

 

Format X-form

Opcode 0xFC000004

Extension Decimal Floating-Point

Operands

• vD
  Target
• vA
  Src A
• vB
  Src B

Example

daddq vd, va, vb

Registers Altered

FPSCR

Related

More in Decimal Floating-Point

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Adds two 128-bit Decimal Floating-Point (DFP) values held in vA and vB, storing the result in vD. The operation follows DFP semantics, respecting the current rounding mode in FPSCR and producing an exact result or DFP overflow/underflow exception as appropriate. The FPSCR is updated with exception flags.

Operation

vD ← vA + vB (DFP arithmetic)
FPSCR ← updated with exception flags (XX, ZX, UX, OX, IE)

Programming Note

The daddq instruction is used for adding two quad-precision decimal numbers. Ensure that the operands are correctly aligned to avoid precision errors. Be aware of potential overflow conditions, which will be indicated in the FPSCR register. This operation requires floating-point privilege level access.