vcmpequd

Vector Compare Equal Doubleword

vcmpequd VRT,VRA,VRB

Compares two vector registers for equality on an unsigned doubleword basis and stores the result in a third vector register.

Encoding

Binary Layout

0:5

VRT

6:10

VRA

11:15

VRB

16:20

199

22:31

Format VC-form

Opcode 0x100000C7

Extension VMX (AltiVec)

Operands

vD
Target
vA
Src A
vB
Src B
VRT
Target Vector Register
VRA
Source Vector Register
VRB
Source Vector Register

Example

vcmpequd v1, v2, v3

Registers Altered

CR6

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Compares two vector registers element-wise for equality on an unsigned doubleword basis (2 64-bit elements) and stores a mask in the destination vector register, with all 1s where elements are equal and all 0s where unequal. When the record bit (.) is set, the CR6 field is updated to reflect whether any or all comparisons are equal.

Operation

for i in 0 to 1 do
  if VRA[i] = VRB[i] then
    VRT[i] ← 0xFFFF_FFFF_FFFF_FFFF
  else
    VRT[i] ← 0x0000_0000_0000_0000
if Rc = 1 then CR6 ← comparison results

Programming Note

When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.