vcmpgtud

Vector Compare Greater Than Unsigned Doubleword

vcmpgtud vD, vA, vB

Compares the contents of two vector registers and sets a result based on whether each element in the first register is greater than the corresponding element in the second register.

Details

The Vector Compare Greater Than Unsigned Doubleword instruction compares each doubleword element of two vector registers as unsigned integers. For each pair of elements, it sets the corresponding result element to all 1s if the first element is greater than the second; otherwise, it sets the result element to all 0s. If Rc=1, it also updates CR field 6 to indicate whether all elements compared true and whether all elements compared false.

Pseudocode Operation

for i = 0 to 7 do
    if (VRA[i] > VRB[i]) then
        VRT[i] <- 1
    else
        VRT[i] <- 0
    end if
end for

Programming Note

This instruction is commonly used in scenarios where you need to compare unsigned integers stored in vector registers. Ensure that the input vectors are properly aligned and that the Rc flag is set if you need to use CR6 for further conditional logic. Be aware that this instruction operates on doublewords, so each element must be 32 bits wide.

Example

vcmpgtud vd, va, vb

Encoding

Binary Layout
4
0
vD
6
vA
11
vB
16
711
21
 
Format VC-form
Opcode 0x100002C7
Extension VMX (AltiVec)
Registers Altered CR6

Operands

  • vD
    Target
  • vA
    Src A
  • vB
    Src B
  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Source Vector Register