vcmpgtud

Vector Compare Greater Than Unsigned Doubleword

vcmpgtud vD, vA, vB

Compares the contents of two vector registers and sets a result based on whether each element in the first register is greater than the corresponding element in the second register.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

711

21:31

Format VC-form

Opcode 0x100002C7

Extension VMX (AltiVec)

Operands

vD
Target
vA
Src A
vB
Src B
VRT
Target Vector Register
VRA
Source Vector Register
VRB
Source Vector Register

Example

vcmpgtud vd, va, vb

Registers Altered

CR6

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Performs an unsigned greater-than comparison of two vector registers on a doubleword-by-doubleword basis (2 doublewords) and stores a mask in the destination vector register, with all 1s where the comparison is true and all 0s where false. No CR or XER flags are modified by this instruction.

Operation

for i in 0 to 1 do
  if vA[i] > vB[i] (unsigned) then
    vD[i] ← 0xFFFF_FFFF_FFFF_FFFF
  else
    vD[i] ← 0x0000_0000_0000_0000

Programming Note

This instruction is commonly used in scenarios where you need to compare unsigned integers stored in vector registers. Ensure that the input vectors are properly aligned and that the Rc flag is set if you need to use CR6 for further conditional logic. Be aware that this instruction operates on doublewords, so each element must be 32 bits wide.